Interesting!

> eg Why do we have HW multipliers & DSP blocks now ? - because they
> are much faster, and lower power, than FPGA fabric solutions.

They are also functions with a broad usefulness in a variety of
applications.
The "faster and lower power" argument can be applied to any piece of IP
you care to name; just for certain functions the transition to hard silicon
makes sense - multipliers, DSP, SERDES, Ethernet MACs, etc. I'm not
quite convinced (yet!) that this is true of MicroBlaze/Nios (yet!).

> > What's wrong with the PowerPC core?
> Let's see - Price, die area....

The price premium of FPGAs with hard processor IP is artificial and it
will be eroded in time. The efficiency of a hard microblaze/Nios in terms
of MIPS/mm^2 will surely, surely be much worse than that of a
processor core that was designed specifically for 90nm.

> > Developing and testing your design in FPGA and then hardening it just
before
> > putting it into mass production is rather like wearing a life-jacket in
the
> > harbour and then throwing it overboard as you set out to sea...
> Which is why you might want move the proven stuff into HardCopy (or
> whatever), and keep the smaller, fluid portion, in FPGA.

"Proven" has always been a relative term. By the time you've "proved" that
your design is perfect, it's most likely a bit late to be ordering mask
sets.

Was your "soft-boundary" idea intended to stay on a single die? That would
certainly be interesting, maybe even useful in limited contexts.

-Ben-