Ben Jones wrote:
>>I don't think
>>that FPGA would ever be the right choice for this type of volume
>>applications. If I plan to sell one million of units, I don't care much if
>>I have to spend one million dollars for ASIC setup, if then one chip will
>>cost one dollar (ASIC) instead of ten (FPGA).
>
>
> Look at the trend in the cost of ASIC setup. Compare that with
> the trend in FPGA gates-per-dollar. Look five years ahead. Now
> consider a choice between ASIC setup of $2M and an FPGA
> costing $3. Which would you choose? Once you've had to do a
> couple of re-spins because your design wasn't quite right first time,
> your FPGA is looking very cheap. And that's before you factor in
> the time-to-market advantage.
>
> Making chips is really hard, and is getting harder. More and more
> companies are realizing that it makes good business sense to let
> somone else take the hit on sub-micron design, qualification and
> testing. This leaves their engineers more time for inventing things
> that actually add value.
>
> Me? I think FPGAs will kill cell-based ASIC within ten years.
> How's that for optimism? :-)

A more interesting question, is when will we see the first MicroBlaze
or Nios in FPGA silicon [not as a soft-cpu]?
They are getting close to stable enough to do this.

Or, when we will see a soft-boundary HardCopy - where you can move
only PART of the total design into ASIC, and keep the rest as a smaller
FPGA.

-jg