Well,
Xilinx shipped me my Foundation 6.3i software update,
and since it has the initial support for Virtex 4,
I installed it and did a design.

Here it is:

====

module top(in_bus,out_bus);
input [15:0] in_bus;
output [15:0] out_bus;

assign out_bus = {in_bus[14:0],in_bus[15]};

endmodule

====

Par Report (trimmed):

Release 6.3i Par G.35
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Thu Sep 02 19:16:08 2004
Loading device database for application Par from file "top_map.ncd".
"top" is an NCD, version 2.38, device xc4vfx12, package sf363, speed -11
Loading device for application Par from file '4vfx12.nph' in environment
Device speed data version: PREVIEW 1.46 2004-07-09.
Device utilization summary:
Number of External IOBs 32 out of 240 13%
Number of LOCed External IOBs 0 out of 32 0%

Total REAL time to PAR completion: 19 secs
Total CPU time to PAR completion: 18 secs

Peak Memory Usage: 105 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

====

Some of the manuals are single page PDFs, that point you to
the web site to get the real thing.

Although you all do HDL designs only, you might want to get
the Schematic Designers library guide as well as the HDL guide,
as the HDL one is 290 pages, and the schematic one is 700 pages.
Most of the extra stuff is stuff you don't need, such as 4 bit
counter macros, but there are also some things that are pretty
interesting that seem to have been left out of the HDL version.
Probably fixed in the next version.

FPGA editor shows lots of interesting new stuff. Still waiting
for a data sheet, as the FPGA editor shows you details of the
forest from the perspective of having your nose pressed against
a huge tree :-) and the library guides is mostly very detailed
for simple stuff like logic and FF primitives, and not nearly
as much info as you might want for the complex stuff.

If this is the sort of thing you like, then you will probably
like this sort of thing.

Philip



Philip Freidin
Fliptronics