Take a step back and study the internal structure of the FPGA you are using.
Become familiar with the logic resources, connectivity, routing, IOB
structure and features, etc. Use FPGA Editor to look inside. Try to
understand what it takes to have a signal from a selected I/O pad reach a
multiplier or a FF or block ram. Then your I/O assignment choices might
come into context.

You might very well find out that only a few of your I/O's are compromised.
If you have, for example, a source-synchronous bus comming into the FPGA
through less-than-ideal channels, you might be able to carefully add a few
reclocking stages to get the signals where they need to go and not have
timing problems.


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

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"Ying Hu" <huying@lastechnologies.com> wrote in message
news:ee88431.6@webx.sUN8CHnE...
> Thanks Marlboro,
>
> I did what you recommended and find FPGA A reaches timing closure with the
automatic pin assignment.
>
> Good lesson for me.
>
> But how can i minimize the effect of pin assignment? I think i should do
floorplanning but i just don't know where to start.
>
> can you recommend me some documents about floorplanning?
>
> Thanks a lot.