Thanks Martin for the valuable
advice.

Actually I already made some improvements to the design by
reducing Level_Of_Logic, adding FFs and giving some attributes.

Since all the 5 FPGAs shares the same design and some of them can
run at a higher frequency, I think floorplanning is a better choice to
meet the timing requirement.

For the current project, No manual floorplanning is done.
After adding those VHDL files and UCF files, I just let ISE to run automatically.

Frankly speaking, I know nothing about floorplanning. Could anyone recommend any book/tutorial on this topic?