Thanks for your help.
I will try to modify this lab to match my needs.
Thanks again.

Eric Crabill <[email protected]> wrote in message news:<[email protected]>...
> Hi,
>
> Go to http://www.engr.sjsu.edu/crabill and download Lab #1.
>
> Eric
>
> Yang-Tzu wrote:
> >
> > Hello everybody,
> >
> > I am trying to use Xilinx's tool, ISE4.1i, to generate the
> > bitstream file from my VHDL designs.
> >
> > If I have three designs named A, B, C. Designs B and C are the
> > components of A. When I using Xst to synthesize C, it could be done.
> > But if I synthesize A, B, and C, errors occured. Therefore, I could
> > have no choice but stop.
> >
> > Could anyone tell me how to using the xilinx command line from
> > synthesize VHDL files to generate bitstream file (or SVF file)? Any
> > Documents about this? I am reading the documents of "Development
> > System Reference Guide" of xilinx, but no good answers.
> > Could anyone tell me the correct design flow or give me an example
> > using command line to synthesize, PAR and generate configuration
> > files?
> > The chip I am using is xc2s100-5pq208.
> > Thanks for any answers.
> >
> > Yang-Tzu