qlyus,
I don't know, but I suspect that this is the case:-
1) The differential receivers works over a very large common mode
range. The common mode voltage probably affects the switching speed
though.
2) The receivers work with very small differential voltages, with the
gotcha being that the smaller the differential voltage the slower the
switching.
3) Xilinx only test the parts to the specifications you quote, because
they can't, or it's too expensive to, check all inputs over all common
mode voltages and differential voltages meet all timing for every part
off the production line.

So, it's physically the *same* receiver, it's just only tested at
the two LVPECL (and the LVDS I guess) points you quote.
Good luck, Symsx.