How fast do you need to sample the ADCs, and how precise do they need to
be? If simple enough, you could do a delta-sigma ADC with the FPGA,
although you still need an analog comparator. You might be able to bias
an LVDS input to act as the comparator, although I have not tried it. The
rest can be accomplished within an FPGA, although if power or cost are
considerations it may require more FPGA than you are willing to support.
I think a two chip solution, one being an FM receiver chip and the other a
microprocessor may be more appropriate.

Tom Hawkins wrote:

> I need a single chip solution for a control system and DSP
> application.
> The primary consideration is board area. The second, cost.
> Here's what I'm looking for:
> - 5V supply and I/O.
> - Embedded ADC (at least 1, preferably 8). Slow rate (50 Hz).
> - Small FPGA fabric. About the size of a small spartan.
> - Embedded block ram (4 KBytes).
> - Flash FPGA. Would like not to have separate config prom.
> - Low I/O count. I only need about 30 pins.
>
> Does anything like this exist? If 5V I/O is not possible, what's
> needed to translate about 12 pins from 3.3/1.2 to 5V?
>
> Also, what's envolved for FPGA based software defined radio? I'd like
> to build an RC (as in radio control airplane) receiver. Most FM
> radios hop between 2 frequencies to encode pulse widths which in turn
> drive the RC servos. So nothing digital. It just needs to extract
> the pulse train from the FM. I would consider trading an FM receiver
> chip for an external high-speed ADC and a larger FPGA if it buys
> enough flexibility.
>
> Regards,
> Tom

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