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Old 01-18-2008, 08:25 AM
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Default Re: Passing verilog Input File as a command line define


"Kevin Neilson" <[email protected]> wrote in message
news:fk6kp8$[email protected]..
> In Modelsim, for example, when you compile, you could use the command:
>
> vlog <verilog_file> +define+INPUT_FILE=config004.txt
>
> and then the $readmemb command would read:
>
> > $readmemb("`INPUT_FILE", config_array);


$readmemb( `INPUT_FILE, config_array);

And depending on the simulator and O/S (UNIX/Linux vs Windows),
the command-line might look something like this:

ncverilog +define+INPUT_FILE=\"config004.txt\"

(The \" are necessary...)


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