On Dec 17, 11:49 am, SB <smartba...@yahoo.com> wrote:
>
> Is it possible that I can generalize the above command,
> so that I can pass the name of the input file to the TB,

There are several ways to do this. The first would be to use a macro
invocation for the filename. Most tools will allow you to provide a
value for a macro on the compile line. The disadvantage of this is
that you will need to recompile your design every time you want to
change the filename (assuming you are using a tool that has a compile
step separate from the simulation step).

As an alternative, some tools might allow you to override the value of
a Verilog parameter from the command line. This could be used to set
a parameter to the filename.

The best alternative would probably be to use the Verilog-2001 system
function $value$plusarg. This would look something like

reg [80*8:1] filename;
...
initial begin
if (!$value$plusargs("INPUT_FILE=%s", filename))
$display("no input file specified");
$readmemb(filename, config_array);
end

This will look for a simulator command line argument that starts with
+INPUT_FILE= and then read the following text into filename assuming a
string format. The big advantage is that you don't need to recompile
the design to change the filename. Minor disadvantages include that
your tool must support this Verilog-2001 feature, and that you have to
decide ahead of time how large of a string to allocate space for in
your variable.