SB wrote:
> Hi there,
>
> I have a Verilog TB that reads from an input file in the following
> way:
> $readmemb("<configuration_input_file.txt>", config_array);
>
> This Verilog TB is used my multiple runs at the same time
> and the configuration_input_file will not be the same for all
> the runs.
>
> Is it possible that I can generalize the above command,
> so that I can pass the name of the input file to the TB,
> using a define such as
>
> $readmemb("INPUT_FILE", config_array);
>
> Then on the command line I will specify something like:
> verilog_simulator <tb_file> <verilog_files> +INPUT_FILE=config004.txt
>
> This is not working for me. What am I doing wrong or is there
> another way to acheive this?
>
> Cheers
> SB

If INPUT_FILE is a parameter, I don't think you should be putting it in
quotes. If it is in quotes it will get treated as an immediate value
and not as a variable. I think you would call the simulator with

> verilog_sim <tb_file> <verilog_files> +INPUT_FILE="config004.txt"

and the $readmemb command would read:

> $readmemb(INPUT_FILE, config_array);

Because strings are treated as any other register, you should be able to
concatenate them like regular registers, like so:

> verilog_sim <tb_file> <verilog_files> +INPUT_FILE="config"
+INPUT_SUFFIX=".txt"

> $readmemb({INPUT_FILE,"00",4,INPUT_SUFFIX}, config_array);

That should work, but alternatively you could use a compiler directive.
In Modelsim, for example, when you compile, you could use the command:

vlog <verilog_file> +define+INPUT_FILE=config004.txt

and then the $readmemb command would read:

> $readmemb("`INPUT_FILE", config_array);

-Kevin