Hi there,

I have a Verilog TB that reads from an input file in the following
way:
$readmemb("<configuration_input_file.txt>", config_array);

This Verilog TB is used my multiple runs at the same time
and the configuration_input_file will not be the same for all
the runs.

Is it possible that I can generalize the above command,
so that I can pass the name of the input file to the TB,
using a define such as

$readmemb("INPUT_FILE", config_array);

Then on the command line I will specify something like:
verilog_simulator <tb_file> <verilog_files> +INPUT_FILE=config004.txt

This is not working for me. What am I doing wrong or is there
another way to acheive this?

Cheers
SB