"mr_camel" <[email protected]> wrote in message news:<[email protected] alkaboutprogramming.com>...
> Hi,
>
> I am working on an ASIC using Synopsys design compiler, Cadence Silicon
> Ensemble, and Synopsys Primetime. Primetime is telling me that my
> register file (8 bit wide 32 registers) is prohibiting me from reaching my
> target clock frequency which is 250 MHz.
>
> Can anyone suggest a way code the register file in Verilog such that this
> critical path is removed?
>
> Thanks,
>
> -Rohit

Even an FPGA can manage this but one would use 16b rams rather than
registers.

You don't say much about the periphery. If the address lines and mux
outputs are flopped, then just a 32->1 mux inside that pipe should be
easy. Sounds like you have siome extra logic paths either in the
address or output path or both.


regards

johnjakson_usa_com