"Kiran" <[email protected]> wrote in message
news:[email protected] om...
> I assume the critical path to be the 32:1 mux for reading from the
> register file. Instead of 32:1 mux try using smaller muxes (like 4:1)
> in a tree structure and place registers between each stage. This will
> increase the read latency.

If muxes *are* being used, perhaps an enable for each register followed by a
wide OR would produce better ASIC-specific results since wide gates should
implement very well.

reg [4:0] Sel;
reg [7:0] RegFile [31:0];

reg [7:0] RegFileRd;
integer i;
always @( RegFile or Sel )
begin
RegFileRd = 32'h0000_0000;
for( i=0; i<32; i=i+1)
RegFileRd = RegFileRd | (Sel == i ? RegFile[i] : 32'h0000_0000);
// 32 5-input ANDs feed 32x8 2-input ANDs followed by 8 32-input ORs
end