There are two distinct phases in bringing an FPGA system to market: the design phase and the debug and
verification phase. The primary tasks in the design phase are entry, simulation, and implementation. The primary tasks in the Debug and Verification phase are to validate the design and correct any bugs found.
The recent advancements in FPGA densities have changed the way we think of design & debug of a FPGA. This camp will focus on what can you do as an engineer to make debugging your FPGA a science rather then an art. It will also introduce to you various tools that you can use to shorten the debug cycle.
Agenda: (Dinner will be provided)
5:00 PM- 6:00 PM: Registration and exhibits (booths from various vendors)
6:00 PM - 6:05 PM: Introductions - Vikash Rungta
6:05 PM - 8:30 PM: Tech Talk
8:30 PM- 9:00 PM: Networking and exhibits (booths from various vendors)
Registration:
FREE! Feel free to bring a friend. Please fill the form below to RSVP using the form below or at Linkedin event url - http://events.linkedin.com/FPGACamp-Debugging-FPGA/pub/136177
Contact us if you would like to:
* Volunteer with us
* Speak or Refer a speaker
* If you are a vendor
- Would like to put a booth - Free
- Demo/Talk about a product (Tell us what and why)- Free ( http://www.fpgacentral.com/fpgacamp/guideline )
- Buy audience some food / drinks
- Give away eval boards, books, kits or goodies to attendees
See you all at the event, it is going to be FUN !!