4th FPGA Camp, Silicon Valley - 6 Apr 2011
This event is sold out (we know its free), but we will not accept any walk-ins. Thanks for the interest.
FPGA Camp is a conference, which brings engineers together to discuss FPGA, mainly NextGen FPGA technology, application, methodology, best practices and challenges. Also provide a location to meet other local FPGA designers to share their stories.
Since its inception in Year 2009, FPGA Camp decided to stay vendor neutral. The attendance is completely FREE and so is putting up a booth. Due to the this approach we soon have been coined as an Open Source conference by Industry leaders like Eric Bogatin, Colin Warwick & Max Maxfield.
Speakers & Moderators
Photos of 4th FPGA Camp
The event will focus on demonstrating key technologies available to bring processor inside the FPGAs. It will provide a glimpse of what to expect in the future, and how to use these great features for your next project.
Check who is attending & RSVP your attendance at LinkedIn: http://events.linkedin.com/Embedded-processors-FPGA-FPGA-Camp/pub/570846
4:00 PM Exhibit booths
4:25 PM Introductions
4:30 PM Tech Talk 1: On Die Instrumentation
5:05 PM Tech Talk 2: PCIe 3.0 case study
5:40 PM Tech Talk 3: Design Choices for Embedded Real-Time Control Systems
6:15 PM Dinner & Exhibit
6:45 PM Vendor Presentation
7:00 PM Panel: "State Of FPGAs - Current & Future" - Moderated by Dave Orecchio, CEO, Gaterocket
8:15 PM Closing
Detailed Topic Brief:
Tech Talk 1: On Die Instrumentation
Presentation describes the challenges of verifying high speed links, and how Altera's 28-nm Stratix V On-Die Instrumentation (ODI) technology overcomes these challenges, and describes the ODI applications.
Presenter - Salman Jiva , Product Marketing Manager, Altera
As Product Marketing Manager for Altera’s high-end FPGA product lines, Salman Jiva is responsible for the technical marketing, positioning and management of high speed SerDes and signal integrity for Altera FPGAs. Prior to joining Altera, he spent six years at Cisco Systems as an ASIC signal integrity engineer for their enterprise line of switches. Mr. Jiva holds an MS in Electrical Engineering from Santa Clara University with a concentration in communication systems.
Tech Talk 2: PCIe 3.0 Controller Case Study
The increased bandwidth of PCIe 3.0 introduces new technical challenges and often leads designers to question and redefine existing PCI Express controller architecture in order to be able to take full advantage of PCIe3.0 performance breakthrough. In this case study, using the practical examples of data path and clock domain crossing, this presentation shows how architectural choices made for a PCI Express controller can have unexpected pitfalls and have a large impact on device including : flow control management, TLP processing, latency, and finally overall performances.
Presenter - Trupti K Gowda , Field Applications Engineer, PLDA
Trupti is a Field Application Engineer at PLDA, the industry leader in the high-speed bus IP market, Trupti K Gowda earned a Bachelor of Engineering degree in Electronics from the University of Pune, India and Masters in VLSI from Polytechnic Institute of NYU, Brooklyn NY. She has been working on high-speed serial protocols for over 3 years.
Many embedded systems have demanding real-time requirements. Typically, there is a software application which interacts with a user or an external system via some dedicated interface while at the same time closed-loop control must react within a certain deadline to arbitrary external disturbances.
We show principles of designing closed-loop Real-Time Control System by taking advantage of inherently parallel processing in Field Programmable Gate Arrays (FPGA). This can avoid real-time problems during system implementation, can facilitate design exploration, and can make production systems more robust and easier to scale. By segregating the timing issues of the real-time control from the user interface, development of control systems becomes easier and more stringent. At the same time, the FPGA building blocks forming the interface and the control algorithm can be easily exchanged and adopted to various requirements. This results in more flexibility and higher degrees of freedom to explore the design space for different control methods and interfaces.
We describe how certain features of modern FPGA devices enable cost-efficient interfaces for Real-Time Control Systems. We also discuss how FPGA design tools and microprocessor IP cores ease the implementation, and how to take advantage of pre-validated system design platforms for hardware-to-software interface design.
Dr. Endric Schubert , Co-Founder, Missing Link Electronics, Inc.
Glenn Steiner, Senior Manager for Xilinx Embedded Processing Solutions, is responsible for the identification, definition and implementation of innovative processing solutions supporting Xilinx customers. Glenn holds a Master of Science degree from UC Berkeley and an Engineer (post Master) degree from Stanford University. His engineering and management work at leading edge companies such as Xilinx, Hewlett-Packard and Trimble Navigation, has given him multidisciplinary experiences in the CAD, IC, personal appliances, robotics, graphics, Internet, virtual reality, medical, analytical chemistry, biotechnical, and navigation industries.
The panel focus would be overall FPGA industry, the trends we are seeing today, and what should be expected in the future.
Moderator: Dave Orecchio , CEO, Gaterocket
Dave has 24 years of semiconductor industry experience at four venture backed companies with a focus on semiconductors, ASIC and FPGA design and development. His leadership brought three of the four companies to successful exits for the investors. Prior to GateRocket, Dave held executive positions in marketing, sales and general management at LTX, Viewlogic Systems, Synopsys, Innoveda, Parametric Technologies and DAFCA.
Panelist 1: Umar Mughal, Product Marketing Manager, Altera
Umar has 11+ years in the PLD industry. Recently Managed the Low Cost Products Marketing team at Altera. Prior to this he held a variety of roles in marketing and applications at Xilinx. He holds a BSEE from Purdue University
Panelist 2: Chris Eddington , Product Marketing Director, High-level Synthesis Products, Synopsys
Chris is the Product Marketing Director for High-Level Synthesis products at Synopsys. Chris has 20 years of experience in ASIC and FPGA design for communications and multimedia products. His previous role was Technical Marketing Director for high speed networking ICs at Mellanox Technologies and prior to that had various roles as Lead IC Designer for VOIP processors, video conferencing ICs, and wireless communications systems. He holds a MS engineering degree from the University of Southern California and an undergraduate degree in Physics and Math from Principia College.
Panelist 3: Gordon Hands , Strategic Marketing Director, low density products, Lattice
Gordon has been working in the programmable logic field since 1995. He has held a number of Product and Strategic marketing roles at AMD, Vantis and most recently Lattice Semiconductor. In these roles he has contributed to the definition and launch of a number of PLD families including the MACH4, MachXO and Mach4000. Gordon is currently Director of Marketing at Lattice Semiconductor with responsibility for Lattice’s Low-density and Mixed-Signal devices. He holds a BEng from the University of Birmingham in England and an MBA from Arizona State University.
Panelist 4: Daniel Platzker , FPGA Synthesis Product Line Director, Mentor Graphics
Daniel Platzker is the product line director for FPGA synthesis in Mentor Graphics design creation and synthesis division. Over the last 20 years, Daniel has held executive positions in marketing, engineering, sales and operations in several high-tech organizations, including the Israeli Department of Defense, Daisy, Tegrity, Castelle and BackWeb. Daniel holds patents in image processing applications and is a winner of the prestigious Israeli Prime Minister Award for product innovation.
Panelist 5: Mark Gustlin , Principal Engineer, Cisco
Mark Gustlin is a Principal Engineer in the Routing business unit at Cisco Systems. He is currently responsible for the definition and development of high end routers at Cisco. He is an active participant in the IEEE and the Interlaken interface community. Mark was one of the editors and active participants in the recently released 802.3ba standard (100GE and 40GE). Mark has over 20 years of experience in data and telecom system development. Mark holds a B.S. in Electrical Engineering from San Jose State University.
Vendor Presentation - Rhino Labs
Introductions - Dave Bursky , Semiconductor Technology Editor, Chip Design Magazine
Dave Bursky, currently the Semiconductor Technology Editor for Chip Design Magazine and the technical editorial manager at Maxim Integrated Products. He has over 35 years of experience as an editor, working for publications such as Electronic Design and EE Times prior to joining Chip Design. Prior to his editorial career he also worked as an engineer for the U.S. Army Electronics Command at Ft. Monmouth, NJ. Additionally, in 2005 he was inducted into the Communications Society Hall of Fame for Lifetime achievement at the City College of New York.
Dave is one of several Electronic Design editors awarded the Jesse H. Neal award for Editorial Excellence. In 1988 he was described by an article in the San Jose Mercury News newspaper as one of the 100 most influential people in Silicon Valley. He has also taught digital logic technology at the former RCA Institute in New York City, and has been a guest lecturer at the Naval Post-Graduate School in Monterey, Calif. Additionally, he has served on the program committees of numerous IEEE and commercial conferences, and has also moderated and organized technical presentation sessions at IEEE and commercial conferences. He has also authored six books on topics ranging from personal computers to semiconductor memories.
Dave holds both Bachelor's and Master's degrees in Electrical Engineering from the City College of the City University of New York (1971 and 1973, respectively).
FOR VENDORS ENQUIRY:
It is a great opportunity for vendors to meet many FPGA engineers & Vendors to interact with each other. Vendors can demonstrate their product and tools to the engineers here. The booths are completely free, so apply now. Contact us at [email protected]
* To qualify to have the free booth you must have a product or tool related to the FPGA.
CALL FOR VOLUNTEERS:
Volunteers are the people who make this event possible, so if you would be interested in volunteering for the event just say so while registering for the event.
And remember attendance for both vendors & users are completely FREE (so bring a friend!!)
For our past events visit http://www.fpgacentral.com/fpgacamp/all