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DPA Circuitry and rx_dpa_locked Signal Behavior in Stratix III Devices

Whitepaper By: 
Altera

The receiver PLL provides eight clock phases to the DPA circuitry. The eight clock phases are separated by 45° and at a frequency equal to the serial data rate. After power up or reset, the DPA circuitry selects an optimum clock phase out of these eight clock phases to sample the received data. The DPA circuitry does not require a fixed training pattern to select the optimum phase. After power up or reset, the DPA circuitry relies on transitions on the received data to select the optimum phase.

Keywords / Tags defining the Whitepaper/Whitepapers: 
Stratix-III , PLL, DPA
AttachmentSize
wp_siii_dpa_lock_behavior.pdf204.12 KB

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