Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers

Technology advancement for the semiconductor industry is largely driven by Moore’s Law in that the number of
transistors in an integrated circuit doubles roughly every two years, as well as demanding a higher data rate for
communication links between devices or systems. Moore’s Law is facilitated by the feature size or process node
shrinkage. Smaller features enable more functionalities, higher operation speed, logic density, integration, and lower power consumption per logic function. A higher data rate is often achieved through using advanced design
methodologies and process technologies, and enables wireline and wireless communication, computer, storage,
military and broadcast electronic systems to send and receive large amounts of data to meet the ever-increasing data transfer or bandwidth demand.
The 65-nm process technology is found in leading-edge products such as microprocessors and FPGAs. The next
generation of these products will use the 45-nm or 40-nm process, available this year. The smaller feature size implies a smaller channel length for a transistor and shorter interconnects for a logic gate, resulting in faster switch time and shorter interconnect transport delay. The results of this process node shrinkage are favorable for logical operation, high density, and high-speed data transmission, as they are optimized for power consumption efficiency.