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Discover How to Design With and Take Advantage of the PCI Express Hard Block in the Virtex-5 FPGA

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The Xilinx 65nm Virtex™-5 LXT/SXT FPGAs are the industry's first to incorporate built-in endpoint blocks for PCI Express® with integrated serial transceivers. Whether you are an expert or just starting out, learn how to easily implement a successful design by exploiting the features offered by the Virtex-5 FPGA with built-in hard block for PCI Express. The integrated end-point block for PCI Express provides the benefits of an ASSP with the flexibility of an FPGA. Join this webcast as we walk through how to implement a memory storage example of Virtex-5 FPGAs and how with this reference design you can leverage and take advantage of the programmable features in an FPGA for backplane, cabled and other types of designs.

Discover how the complete Xilinx solution for PCI Express including the Virtex-5 FPGA Development Kit will quickly and efficiently get you started on a Virtex-5 design using PCI Express.

In this webcast, attendees will learn how to:

* Implement a Virtex-5 FPGA design using the PCI Express hard end-point block
* Use the reference design in an application
* Take advantage of the pre-verified IP, high-performance, low power offered by the hard IP block for PCI Express and save up to 10K logic cells in the FPGA fabric
* Accelerate time to market with the PCI Express technology and Xilinx Virtex-5 FPGA Development Kit

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