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Optimizing DSP Algorithms for FPGA Implementation

Webcast Vendor: 
Synplicity, Inc.

FPGAs offer a wide range of cost/performance for implementing DSP algorithms. Finding the optimal implementation usually involves exploring the tradeoffs between fully parallel vs. serial architectures of the algorithm and will be highly dependent on the available resources, speed, and architecture of the FPGA device. This e-cast will explore how these optimizations work and how they can be applied automatically to high-level algorithm models using Synplicity's Synplify DSP tool. The seminar will include examples in wireless communications and will benefit HW and system engineers who are interested in:

- Methods to rapidly describe algorithms and explore speed/area optimization
tradeoffs
- Creating algorithms and IP that are easily portable and optimized across
vastly different FPGA technologies

Webcast Tags/Keywords: 
DSP, Algorithms, FPGA Implementation

Comments

Tony George (not verified)
August 17, 2008 - 11:50pm

H.264 Video Codec on FPGA

Hardware video encoders & decoders are efficient way of implementing performance oriented, low power Video Codecs. The hardware have high computational and memory bandwidth capabilities that are essential to real-time image/video processing systems, when compared with DSP processors. The products like Digital video recorders, Video wireless devices, Video surveillance systems, Hand held HDTV video cameras, requires low power high performance implementation. The important step towards this realization is to prototype the Codec in FPGA.

http://drtonygeorge.com/Video/h264/h264_rtl.htm


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