Low Power Architecture Exploration for ASIC Algorithm Implementation

With today's advanced low power design requirements it is becoming more and more critical to have proper insight into power consumption early in the design flow. Algorithm and datapath-intensive designs often have architecture tradeoffs which have huge impact on the power profile of the implementation. Thus it is important to properly estimate the power consumption of these alternate architectures quickly and accurately, in addition to analyzing the timing and area results. This webinar will demonstrate using the Synphony high level synthesis tool to do architectural power exploration within days of a having a high level algorithm model in MATLAB or Simulink. The analysis includes timing, area, and power consumption of various multi-rate architectures using Design Compiler and PrimeTime-PX. This seminar will illustrate how to:
- Synthesize multiple architectures from high level models and MATLAB code
- Use MATLAB scripts and Synphony HLS to quickly generate testbenches for activity data (SAIF) and power analysis
- Explore the power impact of different multi-rate clocking strategies
- Optimize memory implementation using compiled memories
- Perform accurate power analysis using advanced features in VCS, Design Compiler, and PrimeTime-PX
- Deliver comprehensive power exploration within days of algorithm high level model availability

Presenters:
Josefina Hobbs
Josefina Hobbs brings nearly 18 years of high-tech design and applications expertise to her role as technical solutions architect, low power solutions marketing, at Synopsys. Hobbs is currently responsible for the deployment of the Eclypse Low Power Solution. While at Synopsys, she has been a key contributor to the successful launch and adoption of Synopsys'advanced multi-voltage capabilities since their inception. Hobbs holds a bachelor's degree in electrical engineering from Duke University and a master's degree in computer engineering from the University of Texas at Austin.

Chris Eddington
Chris Eddington is the Product Marketing Director for High Level Synthesis products. Chris has 20 years of experience in ASIC and FPGA design for communications and multimedia products. His previous role was Technical Marketing Director for high speed networking ICs at Mellanox Technologies and prior to that had various roles as Lead IC Designer for VOIP processors, video conferencing ICs, and wireless communications systems. He holds a MS engineering degree from the University of Southern California and an undergraduate degree in Physics and Math from Principia College.