Achieving Predictable Success in FPGA Design
In this concise series of three technical webinars presented by the Synplicity Business Group (SBG) you can learn how FPGA Design can be made more productive and predictable.
FPGA designers can always beat their ASIC-using colleagues to a working design in silicon but most manage without a system-level model, a timing closure methodology or a verification strategy. The risk in cutting these corners has usually been balanced against the reward of getting the design to market more quickly. Leading-edge FPGA users have realized that the risk-reward ratio is no longer scalable. They are adopting more powerful, more productive and more predictable design and verification techniques.
This three part on-demand webcast series will introduce Synopsys tools for serious FPGA users, including model-based algorithmic design, IP integration tools, tightly coupled constraint and analysis environments, integrated synthesis and placement, and on-board assertion-based verification linked to RTL simulation.
* Part 1: Synthesis and Timing Closure
* Part 2: Algorithmic Model-based Design
* Part 3: FPGA Design Verification