Static Timing Analysis Techniques for FPGAs

Static Timing Analysis (STA) is an important step in analyzing the performance of a design. Lattice's ispLEVER STA tools support both pre- and post-layout STA and constraints setting. STA is much faster than timing-driven gate-level simulation and does not require stimulus vector generation. Unlike dynamic analysis, the quality of the static approach is independent of the quality of stimulus vectors. This webcast covers concepts and techniques of STA and practical examples including sample reports, describing timing exceptions, multicycle paths, and hold-time analysis.