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Easier UVM: Functional Verification for Mainstream Designers

The Easier UVM webinar provides an introduction to the guidelines for learning and using UVM, the Universal Verification Methodology for SystemVerilog. It is aimed at mainstream designers rather than power users specialising in verification. The webinar comprises two sessions, on successive days, each session being one hour long.


Web page:


Schedule and Registration:

This webinar will be broadcast twice, at convenient times for international audiences. Please review the times listed below and register for the most appropriate option to your time zone.

For North America (also UK and Europe if late afternoon preferred)

  • Session 1: Monday November 7Time: 9am-10am (PST) 12pm-1pm (EST) 5pm-6pm (GMT - UK)
  • Session 2: Tuesday November 8Time: 9am-10am (PST) 12pm-1pm (EST) 5pm-6pm (GMT - UK)

Register Now

For UK, Europe and Asia

  • Session 1: Wednesday November 9Time: 9am-10am (GMT - UK) 10am-11am (CET) 2.30pm-3.30pm (IST)
  • Session 2: Thursday November 10Time: 9am-10am (GMT - UK) 10am-11am (CET) 2.30pm-3.30pm (IST)

Register Now


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