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Learn How FPGAs Interface with DDR3 SDRAM

Webcast Vendor: 
Altera

Stratix III I/Os deliver the features required for the latest generation of double data rate memories. These features include:

Leveling, which is required for DDR3 SDRAM DIMMs and not offered by competing FPGAs;
Dynamic on-chip termination, for proper line termination;
Variable input and output delay, for de-skew; and
31 registers behind each I/O pin, to handle all double data rate needs.
In only two years, it's expected that implementing DDR2 will be more expensive than implementing DDR3. If you're starting system designs today that will be in production in 2009 or later, you should consider DDR3 for its cost and power advantages. View this net seminar to understand how DDR3 works and what's required in an FPGA to effectively implement DDR3.

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