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Gigabit Channel Design Guidelines
Though high-speed serial links increase data throughput and reduce the number of traces on a board, a different set of challenges arise when designing these systems. This seminar provides useful guidelines and techniques when designing a high-speed channel. The seminar will cover a channel model case study that includes how to address the challenges of designing at high data rates (BGA breakout, crosstalk, vias, DC block capacitor, and an SMA connector). These challenges are tied in and are implemented in a complete end-to-end channel simulation.
At this net seminar, you'll learn how to:
Address high-speed channel design challenges
Analyze modeled and simulated high-speed interconnects
Employ a simulation environment for an end-to-end channel
Who Should View
System architects
Hardware and system design engineers
FPGA developers
Signal integrity engineers
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Upcoming FPGA Events
- IET & GSA International Semiconductor Forum London, U.K.(Event or Conference)(3 days)
- High-Speed Interconnects - San Jose,Ca(Event or Conference)(3 days)
- 11th Embedded Systems Expo (ESEC) - Tokyo, Japan(Event or Conference)(3 days)
- 7 Habits of Successful FPGA Design Workshop - San Jose, CA(Event or Conference)(10 days)
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