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Dynamically Reconfigure Transceivers for Multiple Data Rates and Protocols in FPGAs
The rapid adoption of high-speed serial interconnect in recent years
has posed new challenges to engineers. The data rates of serial
protocol and proprietary protocol standards are doubling and
quadrupling to keep up with the ever increasing bandwidth requirements
of today’s applications. At the same time, new serial protocol
standards are ratified to address new market requirements.
Designers are faced with the challenge of designing systems that
support the newer and faster serial protocols while continuing
to support slower legacy versions. Until now, design engineers had to
design with multiple ASSPs and boards to support different data rates
and protocols.
Dynamic reconfiguration delivers an elegant solution to this
challenge. With dynamic reconfiguration, Stratix II GX FPGAs with
embedded transceivers are the Swiss Army Knife of high-speed serial
protocols.
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