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Cut Power 100X Using CPLD Coprocessors in Portable Applications
See how designers of low-power, portable electronic products can cut their design’s power consumption by 100X with the new “zero-power†MAX IIZ CPLDs. This 30-minute webcast gives concrete examples on how to use CPLDs as coprocessors to manage and reduce power consumption in portable applications.
In this webcast, you’ll learn:
How a CPLD can be used as a low-power media coprocessor to reduce system power by as much as 100X
Nine standard system functions where using a CPLD can reduce power in portable applications
Three specialized applications that will benefit from using CPLDs
How to use the zero-power features of Altera’s new MAX IIZ CPLDs
How to get a free MAX IIZ demo board
Who Should Attend
Designers new to programmable logic or new to Altera
Consumer electronic product design engineers
Engineering and technical managers
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FPGA Central is a website bringing the FPGA (Field Programable Gate Array), CPLD , PLD, VLSI community together at one central location. Some Keywords: FGPA, FPGA, EDA Tools, FPGA Design, Central, Programmable logic, LUT, VLSI, SoC, Journal
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