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Power Implications of Implementing Logic Using FPGA Embedded Memory Blocks
September 10, 2008 - 4:03pm — scottcOn-chip user memory has become a common resource on modern FPGAs. This memory comes in the form of configurable Embedded Memory Blocks (EMB). EMBs are very area efficient for implementing designs
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Signal Integrity and High Speed System Design 3-day course with Lee Ritchey
IDA, Kalvebod, Brygge 31-33 in Copenhagen
The event is organized in close cooperation between Axcon and E-gruppen, IDA.
This highly practical course is designed to take the student through the entire process involved in designing and fabricating high speed PCBs. It begins with the fundamentals of electromagnetic fields and the behavior of transmission lines that are the basis for all high-speed signaling. From there, it examines all of the aspects of high-speed design leading to the development of a robust set of PCB design rules that accounts for power subsystem design, routing rules and design of PCB stack-ups as well as the fabrication rules needed to balance performance against cost and manufacturability.
The materials and examples used in this course are drawn from actual designs of high speed systems in current manufacture. These examples range from video games to terabit routers and cover the complete range of designs. The design process presented is based on many years of completing designs that are "right the first time". Students are shown many ways to improve their design process so that designs meet this objective. Reliable methods for controlling and containing EMI will also be thoroughly covered.
Part of the last day provides the participants with a unique opportunity to get specific input and solutions to pre-submitted design challenges. We encourage the participants to describe one or two specific design challenges, and submit it for Lee Ritchey to specifically address during this session!
This course addresses the most common high speed problems, including:
* Failures from crosstalk and reflections
* Problems related to time delays in PCB traces
* EMI failures
* Failures stemming from poor power system design
* Failures related to poor IC package design
This course places special emphasis on very high speed differential signaling protocols such as XAUI, Hypertransport, PCI Express, Infiniband, SATA, SSCSI and others that are the backbone of modern computing. Actual circuits are built and tested and then modeled to correlate modeling techniques. The topic of how to design power delivery systems capable of supporting these protocols is also addressed.
Prerequisites
Any engineering professional who works with high speed design will understand the materials presented. No advanced mathematics are required.
Price: DKK 14.500 per person (EUR 1.952).
Register before October 10th for only DKK 13.000 per person (EUR 1.750).
Prices are excl. 25% Danish sales tax/VAT (moms).
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- 2008 International Conference on ReConFigurable Computing and FPGAs (ReConFig'08) - Cancun, Mexico(Event or Conference)(1 day)
- SYSTEM VERILOG ASSERTIONS :: METHODOLOGY AND LANGUAGE TRAINING(Event or Conference)(2 days)
- SystemVerilog Assertions Language and Methodology Overview Seminar (Event or Conference)(14 days)
