Platinum Sponsor
Featured Article
ESC - Embedded System Conference - Silicon Valley, CA
Apr 26 2010 8:00 amApr 29 2010 6:00 pmWhere:The San Jose McEnery Convention Center, San Jose, CAESC is the fastest-growing embedded event in the world, with events happening year-round in locations as Silicon Valley, Boston, India, the UK and France.
FPGA Poll & Survey
Planet FPGA - All FPGA blogs at one place
Tutorial
OHO Elektronik GOP Sereis CPLD/FPGA Modules
The GOP module series are mini modules composed of a CPLD or an FPGA device with a PAL (programmable array logic) / GAL (generic array logic) compatible 24 pin DIL (dual in-line) footprint.
Features
- Small module with a 24 pin DIL plug
- Clock oscillator 49,152 MHz
- Upgrade from PAL / GAL devices
- Powerful replacement for PAL/GAL devices
- Direct use in 20/24-pin DIL socket
- Inputs are 5Volt-tolerant and outputs are optionally 5V CMOS compliant
- Large user memory: 512kByte SRAM, 8Mbit SPI Flash
- On-board quartz oscillator
- Easy diagnosis via 9-pin header (attach oscilloscope or logic analyzer)
- 100% compatible with Xilinx ISE software
Upcoming FPGA Events
- Accelerating Custom IC Layout with IC Station - San Jose, CA(Event or Conferences)(4 days)
- RocketLaunch webinar(Webcast)(6 days)
- How Physical Implementation realizes Power Intent Web Seminar(Webcast)(11 days)
- U2U - User 2 User conference - Santa Clara, CA(Event or Conferences)(18 days)
- RocketLaunch webinar(Webcast)(25 days)
Copyright 2008 @ FPGA Central. All rights reserved.
FPGA Central is a website bringing the FPGA (Field Programable Gate Array), CPLD , PLD, VLSI community together at one central location.
Some Keywords: FGPA, FPGA, EDA Tools, FPGA Design, Centeral, Programmable logic, LUT, VLSI, SoC, Journal
Terms Of Use | Privacy Policy | About Us | Add to Site | Advertise with Us | Blog | Feedback | Powered By Lamingo Creator of eLagaan
  