World's 1st FPGA Portal

• Xilinx FPGA BASED I/O card
• 64 or 48 I/O BITS (4I34/4I34M)
• 5V tolerant I/O
• 24 mA output drive
• Full 16 bit PC104 I/O interface
• Interrupts and DMA support
• Many I/O functions supplied
• 6 or 8 LED status indicators
• Source supplied for all functions
• FPGA downloaded from host
• Low power consumption
• Made in USA - local support
• 2 year warranty
The MESA 4I34 is a general purpose All I/O bits are 5V tolerant and can sink
programmable I/O card for the PC/104 bus. The 24 mA. Pullup resistors are provided for all pins
4I34 uses a 100K or 200K gate Xilinx FPGA for so that they may be connected directly to optoall
logic, so it is truly an “Anything I/O” card. isolators, contacts etc.
The FPGA is downloadable from the The 4I34 is available in 2 versions, the
PC/104 bus side, allowing creation of almost any 4I34 with 64 I/O bits and the 4I34M with 48 I/O
kind of specialized I/O function, even including bits. The 4I34 uses two 40 pin connectors with
micro-controllers in the FPGA. proprietary pinouts, while the 4I34M uses two 50
Several pre-made functions are provided,
including a 64 channel event capture card, a 64
bit parallel I/O card with 16 bit host interface, an 6 (4I34) or 8 (4I34M) LEDs are available
8 channel host based servo motor controller, a 4 for circuit debugging or circuit status information.
channel micro-controller based servo motor Configuration decode can be at 210H
controller (micro-controller CPU built into FPGA), 220H or 230H. Configuration decode can be
and a 8 channel, 32 bit timer counter card disabled after FPGA is configured to reclaim I/O
capable of running at 100 MHz. space.
VHDL source is provided for all examples A 50 MHz crystal oscillator is provided as
and custom I/O functions can be provided on a a system clock. Higher frequencies can be
contract basis. generated by the PLL built into the FPGA.
pin connectors with I/O module rack compatible
pinouts and interleaved grounds.