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PROC2S180
STRATIX-II 180
May replace an ASIC on customer Prototyping environment.
Stand-alone or as Daughter Board.
Largest FPGA - Smallest Foot print.
Supported by Gidel’s PROC Development Kit.
Four level memory structure:
Up to 930 M512 RAM blocks ( 32 x 18 bits).
Up to 768 M4K RAM blocks (128 x 36 bits).
Up to 9 MegaRAM blocks (4K x 144 bits).
32MB DDR II memory with innovative controller
- up to 16 Ports.
User's I/Os available through:
4 daughter card connectors (up to 254 I/Os).
SCSI-5 connector (up to 60 I/Os and 2 clocks).
complete clock management solution with its hierarchical clock structure.
ASIC replacement on customer Prototyping environment.
As you make your prototyping/demo board add 4 connectors around the ASIC. Before getting the ASIC and even before tape-out you may put your logic on the PROC2S Daughter board test and demo your full system.
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