Product Category: 
Development Boards & Kits

Virtex-II-Pro XC2VP30-6, Ethernet 10/100/1000, Infiniband, Fiberchannel

Product Description: 

The Virtex-II Pro Development Kit from Avnet Electronics Marketing offers system level development on a highly advanced hardware platform. The Xilinx Virtex-II Pro family, based on the extremely successful Virtex-II architecture, provides a unique environment for developing high-performance microprocessor and I/O intensive applications. The embedded 32-bit IBM PowerPCâ„¢ RISC processor delivers over 420 Dhrystone MIPS at 300 MHz, with a high-bandwidth interface to on-chip programmable logic. Additionally, Rocket I/Oâ„¢ 3.125 Gbps transceivers support emerging connectivity standards.

Key Features

Xilinx Virtex-II Pro XC2VP7-FF896, XC2VP20-FF896, or XC2VP30-FF896 FPGA
Two HSSDC2 connectors (InfiniBand, user may replace with Fibre Channel)
Receptacles for 2 SFP modules (Gigabit Ethernet, Fibre Channel, InfiniBand)
32-bit PCI Mezzanine Card (PMC) connectors
Four 140-pin general purpose I/O expansion connectors (AvBus)
Micron DDR SDRAM SODIMM (128MB expandable to 1GB)
Micron Mobile SDRAM (two 8Mbit x 16 devices, 32MB total)
Cypress asynchronous SRAM (512Kbit x 32, 2MB total)
Intel StrataFlash® (16MB total)
Compact FLASH card
National 10/100/1000 MBit/s Ethernet PHY
RS-232 serial ports
PCI bridge - Xilinx Spartanâ„¢-IIE XC2S300E-FG456 FPGA
Windows based GUI interface
Configuration or file transfer & system control
Universal PCI connector (32-bit or 64-bit slot compatible)
Support for both 3.3V and 5.0V PCI signaling
Power supply daughter card (+3.3V and +2.5V rails @ 14A total)
50 Watt AC/DC +5.0V power supply
National linear regulators
Bridge (Spartan-IIE)
Xilinx PROM XC18V02-VQ44
In-system programmable PROM
Target (Virtex-II Pro)
Xilinx System ACEâ„¢ CF
FLASH or SRAM via PCI and Windows application
Target Applications

Packet switching
Network security
Storage area networks
Servers and super computers
Video computing/transmission
High-speed serial interfaces (RapidIO, FiberChannel and Hypertransport)

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