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Viterbi Decoder, (IEEE 802-Compatible)

IP Vendor: 
Xilinx
IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Communication and Networking
IP Supported FPGA Device: 
Spartan-3
Spartan-IIE
Virtex
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-E
Virtex-II
Virtex-II Pro
IP Description: 

"The IEEE 802-Compatible Viterbi Decoder module was jointly developed by L-3 Communications and Xilinx. The core reaches OC3 (155 Mb/s) data rates and higher. It has a fully synchronous two-clock version for low latency, small size, and low power dissipation. It also has a fully synchronous one-clock version for rates above 155 Mb/s. The core has parallel radix-2 architecture for high speed and compact size. It supports soft decision input data with parameterizable width. The core uses the industry-standard constraint length of k=7 with G0=171 and G1=133. The two-clock version has a traceback length of 48 or 96. The one-clock version has a traceback length up to 126. The Best State feature in the traceback improves the Bit Error Rate (BER) by up to 0.2 dB compared to Qualcomm's Q1900 device. It has normalization output and supports puncturing through an external interface. It's available as VHDL source code and as a fixed netlist.

Device Family Support

Virtex-4 FX

Virtex-4 FX

Virtex-4 SX

Virtex-II Pro

Virtex-II

Virtex-E

Virtex

Spartan-3

Spartan-IIE

Key Features

Uses the industry-standard constraint length 7, (G0, G1)=(171,133) or (133,171) compatible with Q1900, DVB, IEEE802.11a, IEEE802.16a, HiperAccess, HiperMan, INTELSAT IESS-308/309

Supports adaptive rate change through puncturing interface

Fully synchronous 2x clock version for reduced latency, lower power dissipation, and half Block RAM size; with adaptive traceback length of 48 or 96

Parameterizable options for soft data input, accumulated path metric and best state widths

Fully synchronous one-clock version for adaptive traceback length up to 126"

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