UTOPIA3 PHY-RX

This IP is one of four that Lattice offers to support Universal Test & Operations PHY Interface for ATM (UTOPIA) Level 3. The UTOPIA Level 3 Transmit Interface is designed for performing transmission of ATM cells in different configurable cell formats from the UTOPIA bus to the Physical (PHY) layer device. The core provides a bridge function between the PHY and ATM layers using a high-speed handshaking mechanism. All UTOPIA Level 3 operation modes are fully supported. These include the "Features
Fully Compatible with ATM Forum UTOPIA Level 3 Specifications
Supports Single-PHY and Multi-PHY Operation Modes
Multi-PHY Operation with Single rxclav signal in Polling Mode
Multi-PHY Operation with Up to 4 rxclav Signals in Direct Status Indication Mode
Configurable 8-, 16-, or 32-Bit Wide Data Path for Both UTOPIA and PHY Bus Interfaces
Configurable Cell Format; HEC or no HEC
User-configurable Polarity for Handshaking Signals
Configurable Number of PHY Device Interfaces
Configurable FIFO Size
UTOPIA Interface Parity Detection Circuitry
Integrates FIFO Rate Matching Buffer Using Internal DPRAM
Independent Clocks for UTOPIA and PHY Side Interfaces
UTOPIA Interface Error and FIFO Full Flag Warnings
PHY Interface Error Detection and FIFO Overflow Control
High-speed Operation; up to 104 MHz"