Poll

What is your preferred platform for FPGA Design Flow ?:

Reed-Solomon Decoder

IP Vendor: 
Unicore Systems
IP Code Language: 
VHDL
IP Type: 
Design
IP Category: 
Communication and Networking
IP Description: 

Reed-Solomon (RS) is an error correcting code that works by oversampling the Galouee’s field polynomial constructed from the data to be coded. It is widely used in data storages, communication systems to recover data from possible errors that occur during disc reading or data transmission respectively. This core implements Reed-Solomon decoder for the 8-bit wide symbols. The core is designed to occupy fewer amounts of logic blocks, be fast and parametrizable.

Main features:

  • 8-bit input and output data busses
  • Fully synchronous and pipelined design using a single clock
  • Symbol width upto 8 bits
  • Counts number of errors corrected
  • Detects condition when the number of errors is too big to be
  • corrected
  • Corrects up to 8 errors per input codeword
  • The size of the codeword can be selected up to 255, this number
  • can be changed dynamically

Facebook  Twitter  Linkedin  Orkut  YouTube      RSS

 

Check out FPGA related videos

Find Us On Facebook