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IEEE 802.16e (WiMAX) LDPC Decoder IP core

IP Vendor: 
Unicore Systems
IP Code Language: 
Verilog
IP Type: 
Design
IP Category: 
Communication and Networking
IP Description: 

Error-correcting coding is an essential tool for enabling reliable communication. Unicore Systems provide an Intellectual Property (IP) core for hardware-efficient implementation of low-density parity-check (LDPC) forward error correcting (FEC) schemes intended for the IEEE 802.16e. The IP core covers the entire WiMAX LDPC specification, in terms of block size and code rate. Block size and code rate can be switched on on a block-by-block basis.
 

The decoder design is fully synchronous on a single input system clock. LDPC decoder uses layered offset min-sum belief propagation technique which converges twice as fast as the standard belief propagation algorithm, resulting in twice the throughput and wasdesigned using sequentially-concurrent architecture. In order to detect that the correct codeword is found, two sets of tests are performed in early stop detection unit after finishing the decoding of each layer. IP core contains input and output buffer to ease integration into user system. The Data Input Interface accepts a set of channel observation data in the form of quantized Log-Likelihood on coded bits (bit-LLRs). The Data Output Interface yields the results in the form of hard decision bits. The decoder IP core allows each frame to be monitored and controlled via dedicated configuration pins. Activating the early stop detection function allows reducing power consumption, as the average number of iterations performed decreases especially at low decoded BER operating points. It also decreases the average latency. It might be used to increase the average throughput of the decoder, provided that the system instantiating the decoder is able to deal with variable decoding delays.

Main features:

  • 19 code length supported;
  • all ratio 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 supported;
  • on the fly change of code length and code ratio (useful for
  • adaptive modulation and coding systems);
  • parameterized input data width 5-8 bit (in compilation phase);
  • parameterized internal data width 6-9 bit (in compilation phase);
  • nearly floating point performance with quantization of 5 input bits
  • and internal computation in 8 bits (less then 0.15 dB from floating
  • point BP with 30 iterations);
  • early stop detection unit ;
  • parallelism degree 96;
  • bit-LLR input
  • decoded throughput up to 168 Mbit/sec (Virtex-4 -12 speed grade).
  • Free LDPC Encoder IP core comes with the Decoder

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