8051/8052 microcontroller

8051/52 soft IP core implements the instruction set and hardware resources of widely used i8051/52 microcontroller. The shortened instruction cycles give the advantages to increase the throughput and minimize the power consumption.

Main features:

• Up to 130 MHz clock frequency (in Virtex2 devices),
• 2, 3, and 4 -cycle instruction periods,
• 970 or 1076 CLB slices, and 1 Block_RAM for i8052 architecture,
• high speed JUMP,CALL,RET instructions and interrupt handling,
• up to 100 user defined Special Function registers can be attached,
• up to 2 Mbytes of outer addressable memory with programmed select impulse width,
• Structure optimized for Xilinx Virtex, SpartanII, Spartan3, Virtex4 and Virtex5
• FPGA devices,
• fully parametrized core. The base hardware volume can be minimized down to 500
• CLB slices depending on resource and/or instruction set utilization.
• Supports different technologies (Xilinx, Altera, Actel).