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UMTS/3GPP Turbo Convolutional Decoder

IP Vendor: 
Xilinx
IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Communication and Networking
IP Supported FPGA Device: 
Spartan-3
Spartan-3A
Spartan-3E
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-5 LX
Virtex-II
Virtex-II Pro
IP Description: 

"The TCC decoder is used in conjunction with a TCC encoder to provide an extremely effective way of transmitting data reliably over noisy data channels. The Turbo decoder operates very well under low signal to noise conditions and provides a performance close to the theoretical optimal performance as defined by the Shannon limit. This version of the TCC (Turbo Convolution Code)decoder is designed to meet the 3GPP mobile communication system specification.
Turbo Convolutional Decoder LogiCORE v3.0 Available Now.

Device Family Support

Virtex-5 LX

Virtex-4 FX

Virtex-4 LX

Virtex-4 SX

Virtex-II Pro

Virtex-II

Spartan-3E

Spartan-3

Spartan-3A

Key Features

Implements the 3GPP/UMTS specification

Core contains the full 3GPP interleaver

Full 3GPP block size range supported: 40 - 5114

Core implements the MAX*, MAX or MAX SCALE algorithms

Dynamically selectable number of Iterations from 1-15

Number representation: two’s complement fractional numbers: Data input: 2 or 3 integer bits and 1 to 4 fractional bits; Internal Calculations: 6 or 7 integer bits and 1 to 4 fractional bits

Sliding window size of 32 or 64

Internal or external RAM data storage with optional memory management unit

Fast Termination option

Support for rate 1/3 or rate 1/5 coded input"

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