Poll

What is your preferred platform for FPGA Design Flow ?:

Tri-Mode Ethernet Media Access Controller (TEMAC)

IP Vendor: 
Xilinx
IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Communication and Networking
IP Supported FPGA Device: 
Spartan-3
Spartan-3E
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-5 LX
Virtex-II
Virtex-II Pro
IP Description: 

"The Xilinx Tri-Mode Ethernet MAC core is a parameterizable LogiCORE ideally suited for use in networking equipment such as switches and routers. The customizable TEMAC core enables system designers to implement a broad range of integrated Ethernet designs, from low cost 10/100 Ethernet to higher performance 1 Gigabit ports. The TEMAC core is designed to the IEEE 802.3 specification and operates in 1000Mbps, 100 Mbps, and 10 Mbps modes. In addition, it supports both half and full duplex operation. In 1000 Mbps mode, the TEMAC core interfaces with industry standard PHY devices through a GMII/RGMII interface. In 10/100 Mbps mode, the TEMAC uses the MII interface. The Xilinx Tri-Mode Ethernet MAC, combined with the Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE, provides a complete and highly flexible solution for the implementation of Ethernet Link and Physical layers. The TEMAC core is delivered through the Xilinx CORE Generator tool and is part of the comprehensive suite of Xilinx Ethernet solutions.

Device Family Support

Virtex-5 LX

Virtex-4 FX

Virtex-4 LX

Virtex-4 SX

Virtex-II Pro

Virtex-II

Spartan-3E

Spartan-3

Spartan-3A/3AN

Spartan-3A DSP

Key Features

Designed to IEEE 802.3-2002 specification

Reconciliation sublayer with GMII/MII or RGMII Interface

Configurable half-duplex and full-duplex operation

Configured and monitored through an optional independent microprocessor-neutral interface

Configurable flow control through MAC Control pause frames; symmetrically or asymmetrically enabled

Optional MDIO interface to managed objects in PHY layers (MII Management)

Support of VLAN frames to specification IEEE 802.3-2002

Optional clock enables to reduce clock resource usage

Optional address filter with a selectable number of address table entries

Configurable support of jumbo frames of any length

Configurable inter-frame gap adjustment

Configurable in-band FCS field passing on both transmit and receive paths"

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