What is your preferred platform for FPGA Design Flow ?:

Ten-Gigabit Ethernet Media Access Controller

IP Vendor: 
IP Target Vendor: 
IP Type: 
IP Category: 
Communication and Networking
IP Description: 


Compliant to IEEE802.3ae-2002 standard
64-bit wide internal data path operating at 156.25 MHz
XGMII interface to the PHY layer
XAUI interface to the PHY layer (using PCS/SERDES external to the core)
Simple FIFO interface with user’s application
Multicast address filtering
Transmit and receive statistics vector
Optional MDIO Controller
Programmable Inter Frame Gap
Full duplex operation
Flow control using PAUSE frames
VLAN tagged frames
Automatic padding of short frames
Optional FCS generation during transmission
Optional FCS stripping during reception
Jumbo frames of any length
Inter frame Stretch Mode during transmission

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