10Gb Ethernet MAC
10G Ethernet MAC Features:
- Full MAC layer and Reconciliation sub-layer implementation compliant with IEEE802.3ae
- PHY error and fault signaling provided by Reconciliation sub-layer
- CRC-32 insertion and checking at line-rate
- 100% 10-Gbps bandwidth through implementation of Deficit Idle Counter (DIC)
- Configurable IPG with DIC from 4 bytes to 256 bytes. Note, 12 bytes is the standard, and the
- default mode.
- Configurable mode for padding insertion and removal.
- Optionally delivered with configurable preamble size and contents.
- Full handling on transmit FIFO underrun and receive FIFO overflow.
- Support for port-based Pause frame generation and reception
- Jumbo frame support (1522-16K bytes)
- Transmit and receive clock and data rate decoupling with programmable asynchronous FIFO
- Transmit and Receive Statistics Vector
- Simple 32-Bit or 64-Bit User interface
Tamba Networks offers a size and latency optimized 10GE MAC w/ PCS. The core is optimized for operation in FPGA architectures.
The user transmit interface is through an asynchronous 32-entry 32-bit or 64-bit wide FIFO.
The control signals are user programmable.
The user receive interface is through an asynchronous 32-bit or 64-bit wide FIFO. The FIFO is controlled by the core, and the user sees a
streaming interface at the user clock rate.
The line side interface is through XAUI, RXAUI or 10gBaseR. The core clock domain runs at 312.5/323 MHz.
The core is delivered as either a Xilinx or an Altera optimized solution. The core is plug-and-play with the chosen vendor’s SerDes system-interface.
The solution works with both FPGA vendor’s middle speed-grade FPGA or faster.