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MPEG-4/H.264 Decoder

SOC MPEG-4/H.264 Decoder
IP Target Vendor: 
Xilinx
IP Code Language: 
VHDL
IP Type: 
Design
IP Category: 
Audio, Video and Image Processing
IP Supported FPGA Device: 
Spartan/XL
IP Description: 

The SOC MPEG4/H.264 encoders and decoders are designed and built based on the SOC single clock driven all-hardware technology. With no embedded microprocessors and embedded software, the encoders and decoders run at a very high speed, which are well suited for real-time high definition (HD) and very high definition (VHD) video compression and decompression. Due to the fact that the SOC encoders and decoders are dedicated hardware engines for MPEG encoding and decoding, they have a much smaller footprint for FPGA placement. An additional benefit is that power consumption is also significantly lower.

MPEG4-AVC/H.264 video encoders and decoders are delivered in the following formats:

For Information, please contact:  [email protected]

 

  • IP cores for Xilinx or Altera FPGAs (licensing or one-time fee purchasing)
  • FPGA driver-chips for FPGAs
  • ASIC chips

The SOC MPEG4/H.264 encoders and decoders are designed and built based on the SOC single clock driven all-hardware technology. With no embedded microprocessors and embedded software, the encoders and decoders run at a very high speed, which are well suited for real-time high definition (HD) and very high definition (VHD) video compression and decompression. Due to the fact that the SOC encoders and decoders are dedicated hardware engines for MPEG encoding and decoding, they have a much smaller footprint for FPGA placement. An additional benefit is that power consumption is also significantly lower.

MPEG4-AVC/H.264 video encoders and decoders are delivered in the following formats:

For Information, please contact:  [email protected]

 

  • IP cores for Xilinx or Altera FPGAs (licensing or one-time fee purchasing)
  • FPGA driver-chips for FPGAs
  • ASIC chips

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