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MPEG-2 Video Decoder IP and Module

SOC MPEG2 Decoder
IP Target Vendor: 
Xilinx
IP Code Language: 
VHDL
IP Type: 
Design
IP Category: 
Audio, Video and Image Processing
IP Supported FPGA Device: 
Spartan-3E
IP Description: 

The SOC MPEG2 encoders and decoders are designed and built based on the SOC single clock driven all-hardware technology. With no embedded microprocessors and embedded software, the encoders and decoders run at a very high speed. This makes it well suited for real-time high definition (HD) and very high definition (VHD) video compression and decompression. The fact that there is the dedicated hardware for MPEG encoding and decoding, the SOC encoder and decoder engines have a much smaller footprint for FPGA placement. An additional benefit is that power consumption is significantly lower.

MPEG2 Video Encoders and Decoders are Delivered in the Following formats:

For Information, please contact:

[email protected]

 

  • IP cores for Xilinx or Altera FPGAs (licensing or one-time fee purchasing)
  • FPGA driver-chips for FPGAs
  • ASIC chips
  •  

The SOC MPEG2 encoders and decoders are designed and built based on the SOC single clock driven all-hardware technology. With no embedded microprocessors and embedded software, the encoders and decoders run at a very high speed. This makes it well suited for real-time high definition (HD) and very high definition (VHD) video compression and decompression. The fact that there is the dedicated hardware for MPEG encoding and decoding, the SOC encoder and decoder engines have a much smaller footprint for FPGA placement. An additional benefit is that power consumption is significantly lower.

 

MPEG2 Video Encoders and Decoders are Delivered in the Following formats:

 

 

For Information, please contact:

[email protected]

  • IP cores for Xilinx or Altera FPGAs (licensing or one-time fee purchasing)
  • FPGA driver-chips for FPGAs
  • ASIC chips

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