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MPEG-2 Video Decoder

MPEG-2 Decoder IP core, from System-On-Chip (SOC) Technologies Inc.
IP Target Vendor: 
Xilinx
IP Code Language: 
VHDL
IP Type: 
Design
IP Category: 
Audio, Video and Image Processing
IP Supported FPGA Device: 
Spartan-3
IP Description: 

 The SOC MPEG2 decoder is a single chip solution that supports multi-stream MPEG2 video decoding in standard and high definitions. It is implemented based on SOC’s proprietary single-clock driven all-hardware technology. The decoder fits into a small footprint FPGA, for example, the low end XIlinx Spartan-6 series, such as the XC6SLX16. All decoding functionality is handled by  hardware: without microprocessors and embedded software. The SOC MPEG2 decoder provides high speed and low power decoding when compared to existing software based technologies. It decodes HD 1080p, 2k, and 4k resolutions in both 4:2:0 or 4:2:2 color sampling at a very low latency in real time.  It is suited for both consumer products and high-end applications such as digital cinema, military, and medical devices.

 
The SOC decoder series can be integrated with SOC’s audio decoding technology to provide an all-in-one decoding solution. SOC also integrates network modules, TCP/UDP-IP and Ethernet MACs into the chip to produce full system-on-chip systems. Customized versions of the product are also available on request.
 

 The SOC MPEG2 decoder is a single chip solution that supports multi-stream MPEG2 video decoding in standard and high definitions (HD). 

4:2:2, very high speed, low latency, low power consumption, small FPGA. 

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