Poll

What is your preferred platform for FPGA Design Flow ?:

Synchronous FIFO

IP Vendor: 
Xilinx
IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Basic Logic
IP Supported FPGA Device: 
Spartan-3
Spartan-II
Spartan-IIE
Virtex
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-E
Virtex-II
Virtex-II Pro
IP Description: 

"The Synchronous FIFO module supports data widths up to 256 bits and memory depths of up to 65,536 locations. Memory is implemented in either distributed RAM or SelectRAMâ„¢.

Device Family Support

Virtex-4 FX

Virtex-4 LX

Virtex-4 SX

Virtex-II Pro

Virtex-II

Virtex-E

Virtex

Spartan-3

Spartan-IIE

Spartan-II

Key Features

Optional count vector provides visibility into number of data words currently in the FIFO

Supports memory depths of up to 65,536 locations

Memory may be implemented in either SelectRAM+ or Distributed RAM

Supports full and empty status flags

Invalid read or write requests are rejected without affecting the FIFO state

Four optional handshake signals (WR_ACK, WR_ERR, RD_ACK, RD_ERR) provide feedback in response to write and read requests in the prior clock cycle"

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