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Standard SDRAM Controller for ispMACH Devices

IP Vendor: 
Lattice
IP Target Vendor: 
Lattice
IP Type: 
Design
IP Category: 
Memory Interface and Storage Element
IP Description: 

This high-performance Synchronous DRAM controller has been optimized for use in Lattice's MACH family of PLDs. This SDRAM Controller is designed to interface to standard microprocessors, independent of the processor type. The design as shown supports two 16MB memory regions configured as 4 M x 32 bits. The Application Note shows the user where changes can be made to support other functions. For instance, changing byte enable inputs and address inputs will change the width and size of this design. This design assumes the reader has experience implementing page mode DRAM systems.

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