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SPI-4 Phase 1 with FIFOs v1.0 (FlexBUS-4)

IP Vendor: 
IP Target Vendor: 
IP Type: 
IP Category: 
Bus Interface and IO
IP Supported FPGA Device: 
Cyclone II
Stratix II
IP Description: 

Optical Interworking Forum's (OIF) compliant SPI-4 phase 1 (compatible with AMCC FlexBUS-4) with FIFO buffers
ATM, packet over SONET (POS), and direct data mapping modes
Single- and multi-link operation, scalable from 1 to 16 links
Programmable per-port bandwidth allocation
Programmable FIFO size with programmable almost empty/almost full thresholds
Programmable burst size
Automatic link selection in the source block based on the source FIFO threshold and flow control information
64-bit data bus width
Parity generation/checking over data and control words
Supports the Altera® AtlanticTM Interface on the user side
Fully synchronous design, exceeds 200 MHz
Fully automatic testbench, including driver/monitor
Easy to use in multiplexer/demultiplexer and bridge functions

The OIF SPI-4 Phase 1 core connects physical layer devices to link layer devices in 10-Gbps ATM, POS, and Ethernet applications. Modelware's SPI-4 Phase 1 core performs the interface functions on both sides of the interface. On the system side, the SPI-4 Phase 1 core connects to a single link or to multiple links or ports via Altera's Atlantic interface.

The Spi4Tx block monitors the source FIFO buffer's fill level and the flow control information received from the opposite side of the SPI-4 interface. If a source FIFO buffer has data and the flow control information for the corresponding channel indicates that it is ready to accept data, the Spi4Tx block initiates a data transfer from the source FIFO buffer towards the SPI-4 interface.

The Spi4Rx block transmits the sink FIFO status information to the opposite side according to the sink FIFO almost-full flags. The Spi4Rx block stores data received for a particular link in that link's FIFO buffer. The Sink FIFO flags indicate to the user the presence of data in the FIFO buffer(s)."

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