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SPI-4.2 Foundation and Manager

IP Vendor: 
IP Target Vendor: 
IP Type: 
IP Category: 
Bus Interface and IO
IP Supported FPGA Device: 
Cyclone III
Stratix II
IP Description: 

SPI-4.2 foundation features:

Object interchange format (OIF)-compliant SPI-4 Phase 2 (compatible with Saturn Group POS-PHY L4)
Fully synchronous design, which exceeds 800 Mbps (400-MHz DDR)
PluriBus 64- or 128-bit user interface for easy integration with user's application or seamless integration with other Modelware cores for bridge and multiplexer/demultiplexer designs
Out-of-band packet signaling with start of packet (SOP), end of packet (EOP), mod, and err on PluriBus user interface
SOP data to most significant bit (MSB) alignment function
Handles continuous back-to-back EOP (2N + 1-byte packets) with shared control words
Low-speed (LVTTL) and high-speed (LVDS) FIFO buffer status interfaces
Hitless bandwidth provisioning
Dual in-line package (DIP)-4 parity generation/checking
Training sequence generation and detection
Normal and high-speed FIFO buffer status channel
SPI-4.2 manager features (in addition to foundation features):

Multi-channel FIFO buffers with programmable size per channel
Automatic sink flow control generation (RStat)
Source flow control processing (TStat), credit management per channel, and source data scheduler
Automatic handling of Maxburst1 and Maxburst2 per channel
Packet segmentation and reassembly (store-and-forward)
SOP/EOP checking
Additional advanced features:

Supports dynamic alignment in Stratix® GX devices
Transmission data packer that reduces or eliminates idle words between packets
User interface with programmable pauses that allow post-burst or post-EOP processing
Several programmable features that take into account different interpretations of the SPI-4.2 specification.
ASIC support"

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