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SPI-3 (PL3) Link Layer Interface, 2-channel

IP Vendor: 
Xilinx
IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Communication and Networking
IP Supported FPGA Device: 
Spartan-II
Spartan-IIE
Virtex
Virtex-E
Virtex-II
Virtex-II Pro
IP Description: 

"The Xilinx SPI-3 Link Layer core gives you a fully compliant Packet-Over-Sonet (POS) solution, which can be quickly integrated into your networking system. Through user-configurable options, the Xilinx SPI-3 core provides maximum flexibility while seamlessly interoperating with industry leading Application Specific Standard Products (ASSPs) to guarantee maximum bandwidth data transfers. The Xilinx SPI-3 core is fully compliant with the Optical Internetworking Forum's System Packet Interface Level 3 (OIF SPI3-01.0) standard, as well as the SATURN(R) Development Group's POS-PHY Level 3 (PL3) interface specification. The SPI-3 core interfaces between the Physical (PHY) and Link layer devices within networking applications. The core communicates between devices using the SPI-3 interface standard, transferring data in excess of 2.488 Gb/s OC-48 line rate and enabling ATM, POS and Gb Ethernet applications. The Xilinx SPI-3 Link layer core has been verified in hardware to interoperate with the PMC-Sierra PHY devices (PM5381, PM3386).

Device Family Support

Virtex-II Pro

Virtex-II

Virtex-E

Virtex

Spartan-IIE

Spartan-II

Key Features

Fully compliant Packet-Over-SONET (POS) PHY Level 3 Link Layer Interface

Complies with OIF-SPI3-01.0 System Packet Interface Level-3 (SPI-3) standard

Aggregate bandwidth in excess of 2.488 Gbps supporting OC-48 line rates

175 Mhz performance in Virtex-II

Supports 2 physical channels (ports) across the PL3 interface

Asynchronous FIFO Interface

Fully verified in hardware for inter-operability with PMC Sierra PHY device S/UNI 2xGE"

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